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Silicon Polishing and Grinding
SOI CMP, Grinding and Edge Profiling
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LED Grinding and Polishing
R&D CMP and Wafer Grinding
Wafer Reclaim
Whole Wafer Sample Preparation
 
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Taipei World Trade Center
Taipei, Taiwan
Sept 8-10, 2010
Booth 319, CMP Pavilion
 
Optics Grinding & Polishing

Strasbaugh is the
Introduction
Strasbaugh's
 
Key Technologies
  • Frontside and backside sample preparation capability
  • Ultra-thin backside preparation process – WholeWaferSuperThinningTM
  • Self-stopping frontside preparation process – WholeWaferDeconstructTM
  • Menu-driven automated process control
  • Advanced carrier technology maintains wafer uniformity and edge exclusion

Applications

  • Oxide
  • Tungsten
  • STI
  • Copper
  • Silicon
  • Flip Chip

Wafer Sizes

  • 100mm to 300mm
  • Notched, flatted, round, and square substrates accommodated
Products
  • nOvation® 300mm Whole Wafer Super Thinning
  • nHance® (6EG) 300mm Whole Wafer Deconstruct
  • nSpireTM (6EC) 200mm Whole Wafer Deconstruct

     
 
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